The technical field of this invention is integrated circuit manufacture and more particularly to effective placement of substrate contacts and well-tie contacts within standard cell type Application Specific Integrated Circuits.
Application specific integrated circuit (ASIC) chips may be divided roughly into two major classes, gate-array circuits and standard cell circuits. Gate Array circuits are formed from a xe2x80x98base-barxe2x80x99 in which all the wafer processing steps up to, but not including, the contact opening step are common to every finished circuit (perhaps hundreds of unique finished circuit functions for hundreds of customers) in every detail of the active devices and their first level of interconnect. Only the contact, via, and metal level masks are unique to a given finished circuit function.
Standard Cell circuits, on the other hand consist of placements of xe2x80x98standard cell libraryxe2x80x99 elements (a NAND gate would be an example) which are interconnected by employing a set of custom designed contact, via, and metal level masks to complete the over-all circuit function connections. All mask levels are unique to a given finished circuit function except for the case where a finished circuit function application might have several slightly differing circuit options required.
This invention relates to the solution of a problem which arises in the design of standard cell circuits, wherein cell standardization limits the efficient use of silicon chip area, and consequently, limits the ability to reduce chip costs by reducing chip area. Specifically, the invention relates to the effective placement of substrate contacts and well-tie contacts within the overall circuit function.
Typically, a conventional standard cell library is generated by an engineer who designs the electrical cell and simulates it extensively to verify full adherence to cell specifications. The cell is then implemented in the layout of a mask set for that cell which conforms strictly to a set of xe2x80x98layout rulesxe2x80x99. The successful fabrication of an ASIC product depends on a quality mask set which has been generated following every detail of the xe2x80x98layout rulesxe2x80x99 for the specific fabrication process being used and obviously depends on the quality of the fabrication process, namely, how well each step is controlled. Toward that end, the design is subjected to extremely intense scrutiny by the use of a computer software verification program which analyzes the design for full compliance to all xe2x80x98layout rulesxe2x80x99.
Layout rules generally contemplate several aspects of the fabrication process and also contemplate the aspects of device usage. In the first area, the fabrication process, it is clear that, as an example, there is a limit to the smallest size of a contact opening. There is also a limit to the spacing between adjacent openings to be made on a given mask level. In the second area, regarding device usage, other factors influence xe2x80x98layout rulesxe2x80x99. A major example of this, and the specific concern of this invention, is the rule regarding the number of substrate contacts and well-ties must be placed within a given chip area or along a given linear direction on the chip.
It is well known that the quality of the isolation between separate components in a circuit depends on the isolation quality of the reverse biased P-N junction diode which separates these components. Circuit requirements demand that the quality of this isolation between components be acceptable even when the isolating diode has almost zero reverse bias voltage applied. Any current flow, parasitic or otherwise, must not be allowed to cause isolation diodes to become forward biased, in which case the isolation effectiveness degrades sharply.
For this reason the contact openings which bias the specific areas in question, are controlled as to the number required in a linear dimension by the layout rules. This control, for example, the maximum separation of substrate contacts in a linear dimension, or the maximum separation of well-ties in a given linear dimension is specified by two layout rules. More precisely, a given process will conventionally have layout rules stating (as an example only):
In a process using standard cells, the typical sequence of design steps is roughly as follows:
A netlist is generated which gives a detailed connection of each of the cells to be used and their detailed connection to one another and to the periphery of the chip.
A software router designs the placement and metal level routing between each and every placement.
The engineer reviews the software generated place-and-route details and interacts with the software to optimize the circuit in one or more repeat passes.
In such an automated environment, it is obviously necessary to limit the decisions which the Software Router must make to those as simple conceptually as possible. This is because the software router has an enormously complex problem to solve to start with, and burdening it with additional computer decisions merely adds to design cycle time and cost.
Consequently, the issue of maximum substrate contact spacing and maximum well-tie contact spacing is normally solved at a lower level in the design, namely at the cell design level. If the contacts required are built into the cells themselves, then the router merely needs to contend with the simpler problem of substrate contact and well-tie spacing in the inter-cell regions. This is much simpler, in general, than incorporating the full adherence to the rule into the router function. Irrespective of the techniques used to determine the number of and placement of substrate contacts and well-ties, the verification software will be used for final certification that the design has met the required criteria.
Unfortunately, solving the substrate and well-tie placement problem at the cell level results in much redundancy, and these contacts become much more numerous and wasting of space than would be the case if they were placed only where absolutely necessary to meet the maximum separation limit. The present invention strikes an efficient compromise based on the statistics of analysis of a variety of design examples. The resulting requirement placed on the router in placing these contacts increases, but only incrementally, and the chip size saving is a clear advantage.
This invention is a methodology supplementing the software router flow in a standard cell based ASIC flow in order to improve layout density of the finished chip function. The density improvement results from a revised approach to obtaining adherence to two crucial layout rules regarding (1) the maximum allowed separation between substrate contacts and (2) the maximum allowed separation between N-well-ties. First, based upon an analysis of a variety of designs having a full complement of substrate and well-tie contacts in the basic cell, certain cells are identified which could be gainfully redesigned with such contacts removed. The size of the redesigned cells is reduced in this manner by a significant percentage. When these redesigned cells are used in a modified implementation of the chip, the router supplemented by the methodology of this invention, achieves a smaller lower cost chip layout and the simple modification to build back into the chip layout any substrate or well-tie contacts needed is a relatively straightforward modification of the overall chip layout flow.